An improved current mode logic latch for high‐speed applications - Kumawat - 2020 - International Journal of Communication Systems - Wiley Online Library
MIPI homepage CMOS prescaler basics
T Flip Flop Explained in Detail - DCAClab Blog
Current-Mode-Logic (CML) Latch | EveryNano Counts
Analysis and Design of High-Speed CMOS Frequency Dividers
Toggle Flip-flop - The T-type Flip-flop
Figure 8 from Design of ultrahigh-speed low-voltage CMOS CML buffers and latches | Semantic Scholar
D FLIP-FLOP
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
Circuit configuration of the proposed NDR-based CML D flip-flop | Download Scientific Diagram
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
High Speed Digital Blocks
NB7V52M - D Flip Flop, 1.8 V / 2.5 V Differential, with Reset and CML Outputs
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
An improved current mode logic latch for high‐speed applications - Kumawat - 2020 - International Journal of Communication Systems - Wiley Online Library
OAK 국가리포지터리 - OA 학술지 - Transactions on Electrical and Electronic Materials - High-speed CMOS Frequency Divider with Inductive Peaking Technique
Toggle Flip-flop - The T-type Flip-flop
An improved current mode logic latch for high‐speed applications
PDF) Design of ultra high-speed CMOS CML buffers and latches | Payam Heydari - Academia.edu
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Toggle Flip-flop - The T-type Flip-flop
Circuit schematic of the RTD/HBT CML-MOBILE RZ D-Flip Flop. | Download Scientific Diagram
Low Power Rail to Rail D Flip-Flop Using Current Mode Logic Structure
